C++ Simulation with Linear Nodal Analysis and Verilog® Modules Using Verilator
Icarus Verilog® Simulation with Linear Nodal Analysis and C++ Modules
Spice Simulation to Support System Level Modeling in CppSim/VppSim
View the frequently asked questions
About the developer of CppSim
Verilog® is well recognized as an extremely useful and versatile language for representing digital systems, and verification of large system-on-chip designs are often done by constructing intricate Verilog® testbenches. However, modelling of analog modules can be cumbersome, and results are not readily utilized within other environments such as Python, Matlab®, or Octave.
VppSim extends Icarus Verilog® by seamlessly incorporating CppSim modules, linear circuit networks with switches, and probe statements for Python, Matlab®, and Octave. Users enter their design within the Sue2 schematic editor, simulate their design, and then view the results within GTKWave, CppSimView, Python, Matlab®, or Octave. Aside from these additions, VppSim runs entirely as a Verilog® simulation and therefore supports Verilog® testbenches, Verilog® behavioral code, and the Verilog® PLI.
When comparing CppSim and VppSim, CppSim is most useful when focusing on the analog performance of a system which includes synthesizable Verilog® code, whereas VppSim is most useful when verifying the digital functionality of a system using Verilog® testbenches and synthesizable or behavioral Verilog® code. The overall framework is designed to allow easy transition between CppSim and VppSim for simulation of a given system, so that users can focus on analog performance versus digital functionality in a seamless fashion.
Just as with CppSim, VppSim allows users to easily share their system descriptions with others. In particular, the same Export tool can be utilized to embed complete libraries within a compressed file that can be sent to others. The same Import tool will intelligently bring in outside libraries while avoid name clashes or redundant import of modules. As such, VppSim provides a simple and elegant means of transferring Verilog® system knowledge in the form of modules and testbenches between users.
Finally, it is important to note that the Windows download for the CppSim Version 5 package automatically includes VppSim, as well. If the user desires to use CppSim and VppSim within the Cadence® framework within Linux, they should click on the Download section in order to obtain the Cadence® version of CppSim/VppSim that is included there.