Provides an intensive overview of the analysis and design of PLLs at both the system and circuit levels with emphasis on CMOS implementations. Key topics include background on traditional analog frequency synthesizers and their building blocks, design and behavioral simulation techniques, digital frequency synthesizers, clock and data recovery circuits, and delay-locked loops. New applications areas such as VCO-based analog-to-digital conversion are also be discussed.

Phase-Locked Loops and their Applications

  • Integer-N Frequency Synthesizers
      • - Overview
      • - System level modeling
      • - Closed loop behavior
      • - Noise analysis
         
  • Advanced Analog Synthesizers, Clock and Data Recovery
      • - Dual-loop synthesizers
      • - Direct digital synthesizers
      • - Fractional-N synthesizers
      • - Clock and data recovery (CDR)
      • - Delay-locked loops (DLL)
         
  • Basic Building Blocks (Part I)
      • - Background (noise figure, matching networks)
      • - Voltage-controlled oscillators (VCO)
      • - Noise in LC Voltage-controlled oscillators
         
  • Basic Building Blocks (Part II), PLL Design
      • - High speed frequency dividers
      • - Phase detectors and charge pumps
      • - Loop filter structures
      • - Classical open loop PLL design
      • - Closed loop CAD-based PLL design
         
  • Advanced Analog Synthesizer Techniques
      • - Modulation
      • - Bandwidth compensation
      • - Quantization noise cancellation
      • - Behavioral simulation techniques
         
  • Behavioral Simulation Exercises
      • - Introduction to CppSim
      • - Fractional-N synthesizer simulation example
      • - Advanced example (selection by attendee)
         
  • Digital Frequency Synthesizers
      • - Advantages and challenges
      • - Time-to-digital conversion
      • - Digitally-controlled oscillators
      • - System level modeling
         
  • Examples of Leveraging Digital Techniques in PLLs
      • - High performance digital fractional-N synthesizer example
      • - Mixed-Signal CDR example
      • - Digital frequency acquisition example
         
  • Advanced PLL Examples (Part I)
      • - Fast offset compensation for CDR limit amps
      • - Fractional-N based DLL
      • - Low-jitter multiplying DLL
      • - Sub-harmonic injection-locked oscillator
         
  • Advanced PLL Examples (Part II)
      • - Optical/electrical phase-locked loop
      • - High speed clock-and-data recovery
      • - VCO-based analog-to-digital conversion
      • - MEMs-based clocking