CppSim has served as a valuable tool in the development of new architectures for custom integrated circuits. The publications listed here are the outcome of research done at MIT in this area by Michael Perrott and his former students, and may be a useful reference for those interested in the CppSim package. In particular, some of the tutorials are based on work described in the publications listed here.
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The joint paper with Kärtner below was published in Optics Letters and is made available as an electronic reprint with the permission of OSA. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited. Copyright OSA (OSA Journals weblink: http://www.osa.org/pubs/osajournals/).
 Min Park, M.H. Perrott, R.B. Staszewski "An Amplitude Resolution Improvement of an RFDAC Employing Pulsewidth Modulation," IEEE Trans. on Circuits and Systems I  Regular Papers, Vol. 58, Issue 11, 2011, pp. 25902603.
 Min Park, M.H. Perrott, R.B. Staszewski, "A TimeDomain Resolution Improvement of an RFDAC," IEEE Trans. on Circuits and Systems II  Express Briefs, Vol. 57, July 2010, pp. 517521.
 Min Park, M.H. Perrott, "A Multiphase PWM RF Modulator Using a VCOBased Opamp in 45nm CMOS," Radio Frequency Integrated Circuits (RFIC) Symposium 2010, May 2010.

Kim, M.J. Park, M.H. Perrott, F.X. Kaertner, "Photonic subsampling analogtodigital conversion of microwave signals at 40GHz with higher than 7ENOB resolution," Optics Express, Vol. 16, No. 21, 13 Oct 2008

M. Park, JW Kim, F. Kaetner, M.H. Perrott, "An OpticalElectrical SubSampling Receiver Employing ContinuousTime ΣΔ Modulation," ESSCIRC 2006 Dig. Tech. Papers, Sep. 2006, pp. 182185

E.A. Crain, M.H. Perrott, "A 3.125 Gb/s Limit Amplifier in CMOS with 42 dB Gain and 1us Offset Compensation," IEEE J. SolidState Circuits, vol. 41, pp. 443451, Feb. 2006.

E. Crain, M. Perrott, "A 3.125Gb/s Limit Amplifier with 42dB Gain and 1μs Offset Compensation in 0.18um CMOS," in ISSCC 2005 Dig. Tech. Papers, Feb. 2005, pp. 232233, 595.

Matthew Park, M.H. Perrott, "A 78 dB SNDR 87 mW 20 MHz Bandwidth ContinuousTime DeltaSigma ADC With VCOBased Integrator and Quantizer Implemented in 0.13 um CMOS," IEEE J. SolidState Circuits, vol. 44, Dec 2009, pp. 33443358

Min Park, M.H. Perrott, "A SingleSlope 80 MS/s ADC using TwoStep TimetoDigital Conversion," ISCAS 2009, May 2009, pp. 11251128.

Min Park, M.H. Perrott, "A VCObased AnalogtoDigital Converter with SecondOrder SigmaDelta Noise Shaping", ISCAS 2009, May 2009, pp. 31303133

M. Park, M.H. Perrott, "A 0.13um CMOS 78dB SNDR 87mW 20MHz BW CT DeltaSigma ADC with VCOBased Integrator and Quantizer," ISSCC 2009 Dig. Tech. Papers, Feb. 2009, pp. 170171

M.Z. Straayer, M.H. Perrott, "A 12bit 10MHz Bandwidth, ContinuousTime SigmaDelta ADC With a 5Bit, 950MS/S VCObased Quantizer," IEEE J. SolidState Circuits, vol. 43, April 2008, pp. 805814

M.Z. Straayer, M.H. Perrott, "A 10bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5bit noiseshaping VCObased Quantizer and DEM circuit in 0.13u CMOS," IEEE VLSI Circuits Symp., Jun. 2007, pp. 246247.


B.M. Helal, C.M. Hsu, K. Johnson, M.H. Perrott, "A Low Jitter Programmable Clock Multiplier Based on a Pulse InjectionLocked Oscillator With a HighlyDigital Tuning Loop," IEEE J. SolidState Circuits, vol. 44, May 2009, pp. 13911400

M.Z. Straayer, M.H. Perrott, "A MultiPath Gated Ring Oscillator TDC With FirstOrder Noise Shaping ," IEEE J. SolidState Circuits, vol. 44, April 2009, pp. 10891098
 C.M. Hsu, M.Z. Straayer, M.H. Perrott, "A LowNoise WideBW 3.6GHz Digital DeltaSigma FractionalN Frequency Synthesizer With a NoiseShaping TimetoDigital Converter and Quantization Noise Cancellation," IEEE J. SolidState Circuits, vol. 43, Dec. 2008, pp. 27762786
 M.Z. Straayer, M.H. Perrott, "An efficient highresolution 11bit noiseshaping multipath gated ring oscillator TDC," IEEE VLSI Circuits Symp., Jun. 2008, pp. 8283.

B.M. Helal, C.M. Hsu, K. Johnson, M.H. Perrott, "A Low Noise Programmable Clock Multiplier based on a Pulse InjectionLocked Oscillator with a HighlyDigital Tuning Loop," Radio Frequency Integrated Circuits (RFIC) Symposium 2008, June 2008.

B.M. Helal, M.Z. Straayer, M.H. Perrott, "A Highly Digital Clock Multiplier That Leverages a SelfScrambling TimetoDigital Converter to Achieve Subpicosecond Jitter Performance," IEEE J. SolidState Circuits, vol. 43, April 2008, pp. 855863.

C.M. Hsu, M.Z. Straayer, M.H. Perrott, "A LowNoise, WideBW 3.6GHz Digital DeltaSigma FractionalN Frequency Synthesizer with a NoiseShaping TimetoDigital Converter and Quantization Noise Cancellation," ISSCC 2008 Dig. Tech. Papers, Feb. 2008, pp. 340,617

B.M. Helal, M.Z. Straayer, GY Wei, M.H. Perrott, "A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling TimetoDigital Converter and Digital Correlation," IEEE VLSI Circuits Symp., Jun. 2007, pp. 166167.

M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s MultiRate 0.25μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and AllDigital Referenceless Frequency Acquisition," IEEE J. SolidState Circuits, vol. 41, Dec. 2006, pp. 29302944

M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, L. Zhang, J.P. Hein, "A 2.5 Gb/s MultiRate 0.25μm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter," ISSCC 2006 Dig. Tech. Papers, Feb. 2006, pp.1276,1285

CM Hsu, C.Y. Lau, M.H. Perrott, "A DelayLocked Loop using a SynthesizerBased Phase Shifter for 3.2 Gb/s ChiptoChip Communication," ESSCIRC 2006 Dig. Tech. Papers, Sep. 2006, pp. 460463

S.E. Meninger, M.H. Perrott, "A 1MHZ Bandwidth 3.6GHz 0.18um CMOS FractionalN Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise," IEEE J. SolidState Circuits, vol. 41, Apr. 2006, pp. 966980.

S.E. Meninger, M.H. Perrott, "A Dual Band 1.8GHz/900MHz, 750kb/s GMSK Transmitter Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise," IEEE VLSI Circuits Symp., Jun. 2005.

S.E. Meninger, M.H. Perrott, "Bandwidth Extension of Low Noise FractionalN Synthesizers," Radio Frequency Integrated Circuits (RFIC) Symposium 2005, Jun. 2005.

J. Kim, F. X. Kärtner, M. H. Perrott, "Femtosecond synchronization of radio frequency signals with optical pulse trains," Optics Letters, vol. 29, Issue 17, Sep. 2004, pp. 20762078.

S.E. Meninger, M.H. Perrott, "A fractionalN frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantizationinduced phase noise," IEEE Trans. Circuits Syst. II, vol. 50, Nov. 2003, pp. 839849

M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27mW CMOS fractionalN synthesizer using digital compensation for 2.5Mb/s GFSK modulation," IEEE J. SolidState Circuits, vol. 32, Dec. 1997, pp. 20482060.

M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27mW CMOS fractionalN synthesizer/modulator IC," in ISSCC 1997 Dig. Tech. Papers, Feb. 1997, pp. 366367, 487.

M.H. Perrott, J.C. Salvia, F.S. Lee, A. Partridge, S. Mukherjee, C. Arft, J.T. Kim, N. Arumugam, P. Gupta, S. Tabatabaei, S. Pamarti, H.C. Lee, F. Assaderagi, "A TemperaturetoDigital Converter for a MEMSBased Programmable Oscillator With < +/ 0.5ppm Frequency Stability and < 1ps Integrated Jitter," IEEE J. SolidState Circuits, vol. 48, Jan 2013

M.H. Perrott, J.C. Salvia, F.S. Lee, A. Partridge, S. Mukherjee, C. Arft, J.T. Kim, N. Arumugam, P. Gupta, S. Tabatabaei, S. Pamarti, H.C. Lee, F. Assaderagi, "A TemperaturetoDigital Converter for a MEMSBased Programmable Oscillator with Better Than +/ 0.5ppm Frequency Stability," ISSCC 2012 Dig. Tech. Papers, Feb. 2012, pp. 206207

F.S. Lee, J. Salvia, C. Lee, S. Mukherjee, R. Melamud, N. Arumugam, S. Pamarti, C. Arft, P. Gupta, S. Tabatabaei, B. Garlepp, H.C. Lee, A. Partridge, M.H. Perrott, F. Assaderagi, "A programmable MEMSBased clock generator with subps jitter performance," IEEE VLSI Circuits Symp., Jun. 2011, pp. 158159

M.H. Perrott, S. Pamarti, E.G. Hoffman, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker, S.Perumal, B.T. Soto, N. Arumugam, B.W. Garlepp, "A Low Area, SwitchedResistor Based FractionalN Synthesizer Applied to a MEMSBased Programmable Oscillator," IEEE J. SolidState Circuits, vol. 45, Dec 2010, pp. 25662581

M.H. Perrott, S. Pamarti, E. Hoffman, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker, S.Perumal, B. Soto, N. Arumugam, B.W. Garlepp, "A LowArea SwitchedResistor LoopFilter Technique for FractionalN Synthesizers Applied to a MEMSBased Programmable Oscillator," ISSCC 2010 Dig. Tech. Papers, Feb. 2010, pp. 244245

E.A. Crain, M.H. Perrott, "A Numerical Design Approach for HighSpeed, Differential, ResistorLoaded, CMOS Amplifiers," IEEE International Symposium on Circuits and Systems (ISCAS '04), May 2004.

C.Y. Lau, M.H. Perrott, "Phase Locked Loop Design at the Transfer Function Level Based on a Direct Closed Loop Realization Algorithm", Design Automation Conference (DAC), Jun. 2003, pp. 526531

M.H. Perrott, M.D. Trott, C.G. Sodini, "A modeling approach for ΣΔ fractionalN frequency synthesizers allowing straightforward noise analysis," IEEE J. SolidState Circuits, vol. 37, pp. 10281038, Aug. 2002.

M.H. Perrott, "Behavioral simulation of fractionalN frequency synthesizers and other PLL circuits," IEEE Design & Test of Computers, vol. 19, pp. 7483, Jul. 2002.

M.H. Perrott, "Fast and Accurate Behavioral Simulation of FractionalN Synthesizers and other PLL/DLL Circuits", Design Automation Conference (DAC), Jun. 2002, pp 498503.
 M. Alhawari, M.H. Perrott, "A Clockless, MultiStable, CMOS Analog Circuit," ISCAS 2014, June 2014, pp. 17641767.
 W. Saadeh, T. Tekeste, M.H. Perrott, "A >89% Efficient LED Driver with 0.5V Supply Voltage for Applications Requiring Low Average Current," ASSCC 2013, Nov. 2013, pp. 273276
 M. Alhawari, N. Albelooshi, M.H. Perrott, "A 0.5V <4uW CMOS LighttoDigital Converter Based on a NonUniform Quantizer for a Photoplethysmographic HeartRate Sensor," IEEE J. SolidState Circuits, vol. 49, January 2014, pp. 271288
 M. Alhawari, N. Albelooshi, M.H. Perrott, "A 0.5V <4uW CMOS Photoplethysmographic HeartRate Sensor IC Based on a NonUniform Quantizer," ISSCC 2013 Dig. Tech. Papers, Feb. 2013, pp. 384385
 M.H. Perrott, R.J. Cohen, "An Efficient Approach to ARMA Modeling of Biological Systems with Multiple Inputs and Delays," IEEE Transactions on Biomedical Engineering, vol. 43, Jan. 1996, pp. 114

M.J. Park, "A 4th Order ContinuousTime ΔΣ ADC with VCOBased Integrator and Quantizer," PhD Thesis, MIT, February 2009.

C.M. Hsu, "Techniques for HighPerformance Digital Frequency Synthesis and Phase Control," PhD Thesis, MIT, September 2008.

M.Z. Straayer, "Noise Shaping Techniques for Analog and Time to Digital Converters Using Voltage Controlled Oscilllators," PhD Thesis, MIT, June 2008.

B.M. Helal, "Techniques for Low Jitter Clock Multiplication," PhD Thesis, MIT, June
2008.

S.E. Meninger, "Low Phase Noise, High Bandwidth Frequency Synthesis Techniques", PhD Thesis, MIT, May 2005.

S. Kuo, "Linearization of a Pulse Width Modulated Power Amplifier," June 2004.

E.A. Crain, "Fast Offset Compensation for a 10 Gbps Limit Amplifier," May 2004.

M.H. Perrott, "Techniques for High Data Rate Modulation and Low Power Operation
of FractionalN Frequency Synthesizers," Sept. 1997.