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CppSim automatically generates, compiles, and runs C++ code corresponding to the schematic design that you create.

Graphical Interface:

Systems are specified and simulated within a schematic editor, Sue2, and results are viewed using a waveform viewer (CppSimView or GTKWave).

Analog modules:

A simple text template for each module is filled in by the user which can make use of a rich set of C++ classes to represent common functions such as filtering, noise, etc.

Digital modules:

CppSim utilizes Verilator to automatically create C++ code corresonding to your Verilog modules, and seamlessly integrates this code into your system simulation.

Linear networks and switches:

CppSim automatically creates a C++ state-space representation of linear networks with switches in your schematic design, and seamlessly includes this code in the simulation.

Verilog Testbenches:

VppSim combines Verilog with CppSim to seamlessly include C++ modules and linear networks with switches with Verilog as specified within a schematic driven framework.

Spice Simulation:

NGspice is included as a standalone tool for transistor level simulations and utilizes the schematic editor and waveform viewer of the CppSim framework.

Postprocessing with Python, MatlabĀ®, and Octave

CppSim simulations are easily read into Python, MatlabĀ®, and Octave to allow seamless postprocessing of your results.

Try it:

Click the Download button to install, and start with the CppSim Primer in the Manuals section to learn how to use the tool.